High Level Synthesis of Pipelined Datapaths

High Level Synthesis of Pipelined Datapaths

Author: Péter Arató, Tamás Visegrády, István Jankovits

The CAD tool PIPE has been developed in response to the increased speed requirement and complexity of ASIC executable tasks. High level synthesis offers more complex ASIC design solutions, now emerging in academic and industrial design environments. In this timely resource, the applicability of the PIPE tool is considered in the context of the field towards hardware / software co--design and system level synthesis.
* Increasing interest in high-level logic synthesis as designs with 200 million transistors on a single chip become commonplace
* Step-by-step tutorial in the CAD tool "PIPE", illustrating the applications potential, including the advantages, drawbacks and benchmark results
* Supplementary CD-ROM including synthesis subroutines and benchmarks
Professional hardware engineers and researchers who are familiar with high level synthesis or related topics would find this to be a valuable reference resource. Also, MSc and PhD students studying or researching high level synthesis or related topics could use the book as a tutorial text to accompany existing works on this rapidly evolving topic.

Contents

Preface.
Introduction.
The Elementary Operation Graph (EOG).
Reducing the Restarting Period.
Synchronization.
Examples for Applying the Algorithms RESTART and SYNC.
Scheduling as Arrangement of Synchronizing Delay Effects.
Allocation.

Combinatorial and Asynchronous Operations.
Multiple-Process Recursive Loops.
Control Principles.
Scheduling Methods.
Examples for Comparison of the Scheduling Algorithms.
The Design Tool PIPE.
Effective Graph Generation.
System-Level Synthesis Principles.
Solved Problems.
Further Reading.
Glossary.
References.
Index.